1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
A dynamic random access memory (1Tr-DRAM) including one capacitor and one transistor (referred to as a cell transistor) has been widely used as a typical semiconductor memory device. However, there is a requirement that the capacitance of the capacitor is not changed even when a circuit is miniaturized, and thus formation of the capacitor is becoming a major hurdle.
Under such a circumstance, a gain cell including two transistors and one capacitor (e.g., see Patent Document 1) has attracted attention as a potential solution for the problem of the conventional 1Tr-DRAM for the following reason. The capacitance of the capacitor in the 1Tr-DRAM is determined by the ratio of the capacitance of the capacitor to the parasitic capacitance of a bit line. In contrast, the capacitance of the capacitor in the gain cell is determined by the ratio of the capacitance of the capacitor to the gate capacitance of a read transistor; therefore, there arises no problem even when the capacitance of the capacitor can be reduced as the size of the transistor is reduced for miniaturization.
A circuit of the gain cell will be briefly described with reference to FIG. 1. FIG. 1 illustrates four memory cells. Among the memory cells, a memory cell including a write transistor WTr_1_1 will be described. This memory cell includes a read transistor RTr_1_1 and a capacitor in addition to the write transistor WTr_1_1.
A source of the write transistor WTr_1_1, a gate of the read transistor RTr_1_1, and one terminal of the capacitor are connected to each other, thereby forming a memory node. Further, the other terminal of the capacitor is connected to a read word line RWL_1, a gate of the write transistor WTr_1_1 is connected to a write word line WWL_1, a drain of the write transistor WTr_1_1 is connected to a write bit line WBL_1, a drain of the read transistor RTr_1_1 is connected to a read bit line RBL_1, and a source of the read transistor RTr_1_1 is connected to a common wiring CL.
Such memory cells are arranged in matrix and connected by write word lines WWL, write bit lines WBL, read word lines RWL, read bit lines RBL, common wirings CL, and the like.